1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a so-called BiCMOS transistor (Bipolar Complementary Metal-Oxide Substrate transistor), in particular, a Bipolar transistor (hereinafter referred to as a Bi transistor) in which a cell is comprised of the CMOS transistor and the Bi transistor formed on a single semiconductor substrate.
2. Description of the Prior Art
Conventionally, a BiCMOS transistor is comprised of a CMOS transistor and a so-called lateral type npn-Bi transistor which are simultaneously formed on a single semiconductor substrate, have almost the same dimensions and are formed in almost the same steps. FIG. 3 shows the structure of a lateral type npn-Bi transistor 30. Of course, the CMOS transistor (not shown) is simultaneously formed on a p-type Si substrate on which the Bi transistor 30 is formed.
In FIG. 3, the Bi transistor 30 mainly comprises a gate portion 33, an n.sup.+ layer emitter region 34 and an emitter electrode 35, an n.sup.+ layer collector electrode pullout region 36 and a collector electrode 37, and a p.sup.+ layer base electrode pullout region 38 and a base electrode 39 through a p well 32 on a p-type Si substrate having LOCOS films 31a, 31b and 31c.
Furthermore, when the n-channel MOS transistor formation region (not shown of the CMOS transistor is subjected to n.sup.+ doping so as to form the source-drain region of the n-channel MOS transisor, a Bi transistor formation region is simultaneously subjected to n.sup.+ doping so as to form the n.sup.+ layers 34 and 36.
When the p-channel MOS transistor formation region (not shown) of the CMOS transistor is subjected to p.sup.+ doping so as to form the source-drain region of the p-channel MOS transistor, the Bi transistor formation region is simultaneously subjected to p.sup.+ doping so as to form the p.sup.+ layer 38.
According to a method for forming a Bi transistor mentioned above, however, (i) the emitter region 34 is patterned by a photolithographic technique. An emitter dimension (size) should have an alignment allowance. Consequently, it is difficult to reduce the emitter dimension.
Furthermore, (ii) the emitter region 34 and collector electrode pullout region 36 are formed with the gate portion 33 interposed between the LOCOS films 31a and 31b. The base electrode pullout region 38 is interposed between the LOCOS films 31b and 31c. Consequently, the occupied area of the Bi transistor formation region may be larger than the occupied areas of the channel regions of the CMOS transistor, i.e., those of the n-channel and p-channel MOS transistor formation regions by the area of the base electrode pullout region 38. As a result, the Bi transistor 30 is made larger than the MOS transistor, so that it is hard to reduce a cell size.
It is an object of the present invention to provide a method for manufacturing a semiconductor device wherein an increase in cost is held down to a minimum and the occupied area of a Bi transistor is at least made small and almost the same as that of each MOS transistor so that a cell size can be reduced in the case where the Bi transistor having high performance is to be formed on a semiconductor substrate, on which a CMOS transistor is formed, in almost the same steps so as to have almost the same dimension as that of the CMOS transistor.